The inventive concepts described herein relate to nonvolatile semiconductor memory devices.
During a data read operation, a large-capacity nonvolatile memory device, such as electrically erasable and programmable read only memory (EEPROM), reads data from memory cells in the unit of pages and serially outputs the read data. During a data write operation, the large-capacity memory device serially receives the data in the unit of one page and writes the received data into memory cells in the unit of pages. In order to perform these data read and write operations, a plurality of row lines, i.e., bitlines are connected to a page buffer including a data latch configured to temporarily latch read data and data to be written.
Data writing of a NAND-type EEPROM is performed with respect to a memory cell included in one bank, among a plurality of memory cells arranged in a matrix of rows and columns. Conventionally, a memory cell of a NAND-type EEPROM is a floating gate-type N-channel MOS transistor. Such a MOS transistor is disposed within a P-well formed on one surface portion of a semiconductor substrate. Floating gate-type N-channel MOS transistors are spaced apart from each other in the P-well.
A floating gate-type N-channel MOS transistor includes source and drain regions, a tunnel oxide layer disposed on a channel region between the source and drain regions, a polysilicon floating gate disposed on the tunnel oxide layer, and a control gate disposed on the floating gate with a dielectric insulator interposed therebetween.
Memory cells in one column are serially connected to constitute a NAND cell string. A first selection transistor is disposed between one end of the NAND cell string and a bitline, and a second selection transistor is disposed between the other end of the NAND cell string and a common source line.
In a data write operation, when data “0” is written while turning on the first selection transistor and turning off the second selection transistor, a voltage of 0 volt is supplied to a bitline. On the other hand, when data “1” is written (e.g., an erase state is maintained), a power supply voltage VCC is supplied to the bitline.
Additionally, a program voltage Vpgm (e.g., 18 volts) is supplied to a wordline WL of a selected memory cell, and a program inhibit voltage Vpass (e.g., 9 volts) is supplied to a wordline WL of an unselected memory cell.
Thus, in a memory cell into which the data “0” is to be written, a voltage is applied between a channel and a control gate to introduce electrons into the floating gate from the channel and a threshold voltage of the memory cell shifts in a positive direction, for example, from a negative voltage to a positive voltage.
On the other hand, in a memory cell into which the data “1” is to be written, a relatively lower voltage is applied between the channel and the control gate to suppress introduction of electrons into the floating gate and the threshold voltage of the memory cell is maintained, for example, in a negative voltage state.
As described above, a NAND-type EEPROM relies on tunnel current to write data. Further, even though write times of all the memory cells are equal to each other, and data write speeds can vary based on the number of memory cells being written.
Ideally, the threshold voltage of a programmed memory cell (e.g., a “0” memory cell) is properly between 0 volt and a predetermined voltage (e.g., 5 volts). In practice, however, the threshold voltage of one or more memory cells may exceed the predetermined voltage. These memory cells are referred to below as over-programmed memory cells.
In a NAND-type EEPROM, during a data read operation, a memory cell becomes an ON-cell by applying the predetermined voltage (hereinafter referred to “read voltage Vread”) to a wordline WL of an unselected memory cell. However, when a threshold voltage of an over-programmed memory cell is higher than the predetermined voltage, the memory cell is maintained at an OFF-cell state. Accordingly, since a current path of a NAND cell string is blocked by the memory cell, data of all memory cells included in a NAND cell string connected in series to the memory cell cannot be read.
For this reason, there have been proposed methods of configuring data writing from the same cycle as a data setting operation for a data write operation, a write verify operation, and a rewrite operation. In a memory cell whose threshold voltage sufficiently rises due to the write verify operation, rewrite data (data “1”) is set to a data latch of a page buffer such that data “0” is not written in the next cycle.
However, in a one-time data write operation (following a first or second data write operation), there may be a case where a threshold voltage of a selected memory cell rises to exceed the predetermined voltage. In this case, in a verify operation, it is determined that data “0” is properly written into the selected memory cell, even though the memory cell may have a threshold voltage which exceeds the afore-mentioned predetermined voltage (i.e, an over-programmed memory cell”). When there is an over-programmed memory cell at a NAND cell string, data of another memory cell connected in series to the over-program memory cell cannot be read, as described above.